At a glance
Cadence is hiring a RTL-to-GDS implementation, Senior Principal Solutions Engineer in Austin, TX. It is a full-time role in Hardware & Semiconductors, asking for at least 7 years of experience, first listed on November 1. The description mentions RTL design and Verilog. Cadence has 99 other openings in the US, 18 of them in Austin, TX. Across all employers on USA Jobs 24 there are 37 Hardware & Chips openings in Austin, TX today; the typical one asks for 7 years and advertises about $194,000 a year at the midpoint.
About this role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer Customers achieve superior performance for their Design PPA Goals. AE's are expected to possess Synthesis (logical and physical), Place and Route (primary focus) , STA / SDC skills and some experience supporting tapeouts. Experience with multivoltage design implementation and clock tree debugging is desirable.
In addition, Solutions Engineers are expected to be able to articulate design methodologies involving Cadence tools and be 'elevator talk' proficient in the full Cadence tool portfolio. Development time will be spent gaining expertise in additional, or specialization tools, broadening focus from product emphasis to methodology, Full Flow Implementation Training, and learning to leverage success . Full Flow Services Projects involves owning block implementation, top level implementation and Signoff focused efforts. Job exposure will be on RTL to GDSII delivery of projects. There's an opportunity to get involved in competitive benchmarking on complex blocks including CPUs, GPUs and DSP cores. These projects involve implementation in multiple technology nodes on standard foundry solutions. If you are looking to gain experience in methodology, product delivery, and working on cutting edge technology, this is the right role for you.
Position Requirements:
* 7+ years experience and a strong technical knowledge of company products.
* Design experience should include ASIC design using industry-standard hardware description languages (Verilog)
* Senior Level Applications Engineer position with Deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) experience and knowledge are required
* Innovate with Low Power and Multi-Voltage Design Techniques working with leading edge Wireless and Mobile Customers
* Senior level Design Engineer position supporting RTL-to-GDS implementation flows using Encounter Digitial Implementation Platform
* Manage strategic customer evaluations/benchmarks on Cadence's front-end solutions to establish technology differentiation and assert Cadence competitive advantages. Multiplex several issues and set priorities and exploit new technologies are essential for success in the position
We’re doing work that matters. Help us solve what others can’t.
USA Jobs 24 copied this listing from Cadence's official careers site on November 1, 2026 and checked it again November 2, 5:17 AM ET. Cadence will never ask you to pay to apply or to buy equipment with a check they send you. If anyone does, it is a scam.
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